JTAG Probes for Xilinx FPGAs


Xilinx Collection

Various Xilinx JTAG probes

Some probes used to program Xilinx devices.

From left to right: Digilent's probe that shipped with their S3 evaluation board, the Xilinx Parallel-III cable, the Xilinx Parallel-IV cable, and Altium’s JTAG probe that connected to a parallel port and provided a second JTAG instrumentation bus. The Altium probe is shown connected to the Digilent S3 evaluation board to test the logic analyzer instrumentation.

A closer look at the internals is further down, but looking back, Xilinx missed an opportunity to put a debugger onto every board at minimal extra cost. Instead, they fleeced their customers for probes and configuration memory. Flipping bits within a byte for the configuration byte-stream was a bit annoying.


Probe Peddler

An Avnet FAE gave me a Virtex FPGA evaluation board during a contracting period in 2000. Much like a dope dealer — to get you hooked. I had to buy a Xilinx Parallel-III Cable JTAG probe, which was not bad considering the free evaluation kit plus downloadable Xilinx tools. That's how the habit started!

Erich's timing was perfect, as the MIPS debug tools were poor and besides an expensive logic analyzer, a FPGA could help.

Avnet Virtex demo board

Xilinx Virtex demo board from Avnet in 2000. Many improvements were made over prior Xilinx devices with the Virtex launch.

Xilinx JTAG probes on the demo board

The JTAG connection on the Virtex demo board with the Parallel-III cable. Unlike Altera, no header was defined, so an array of wires had to be attached to the target. Luckily there were not many.

The same probe had different fly leads for the older connector on the top left.


Xilinx Parallel-III Cable

As the years passed, the PC parallel port became endangered with the various settings and electrical interfaces causing compatibility problems. However, USB would increase entry barriers for device drivers as well and interface pods. How would you debug USB without some special scope attachment?

With the extinction of the parallel port, the Parallel-III cable also became endangered, so why not open it up?

Xilinx Parallel-III Cable board

Xilinx Parallel-III Cable board. So little for so much!

Student's Parallel-III version

A post-grad student quickly put together a Parallel-III Cable compatible board.

Warwick's Xilinx Parallel-III Cable board

Student's Xilinx Parallel-III Cable compatible board.


Xilinx Parallel-IV Cable

Before the Parallel-IV cable was tested, a USB version was ordered with some Virtex-II Pro boards. However, the first Xilinx USB based probe sucked the life out of the laptop and shut down the USB port on over-current. The probe was returned for a credit and we used the Parallel-IV cable. This was in an academic setting with full tools and software packages. There are no internal photos, however, the probe is probably in a drawer hanging onto its asset number for the annual audit.

On the right, an Avnet Virtex-II Pro evaluation board with Xilinx Parallel-IV cable used to configure the FPGA and debug the PowerPC. The PowerPC debugger spent more time in the weeds than Xilinx would care to admit. We moved to GreenHills SlingShot probes with another Avnet PowerPC board (AMCC GX440) and put the Xilinx boards into the drawer as they failed to compile previous projects when upgrading the tools from version 6. Avnet never took out the 405 PPC trace port on the Virtex-II Pro!

Virtex-II pro with Parallel-IV cable

Parallel-IV connected to Virtex-II Pro board


Digilent Parallel-III compatible probe

The Digilent S3 board (under Products → FPGA boards → S3 Board). When updating this page, we noted that National Instruments acquired Digilent in January, 2013, but some months later, the S3 board was still available at $169. The S3 board shipped with a Parallel-III compatible cable with predefined pinouts connecting to the board without flying leads. Exact details have been erased from that section of the brain, but the board with programmer was not much more than Xilinx' price for the cable. Several boards were purchased at excellent academic pricing.

Digilent Parallel-III compatible Cable board

Digilent Parallel-III compatible board. So much for so little!

Digilent Parallel-III Internals

Another victim of the parallel port, the Digilent probe was put onto the operating table to expose its internals before being sent to a landfill.

Digilent's Xilinx Parallel-III compatible board

Digilent's Xilinx Parallel-III compatible board. The DB25 shell attached to a PC parallel port, with the interface electronics on the other end of the cable on a small board encased in heat shrink sleeving.


Altium JTAG probes

We purchased the full Altium development software package many years ago when Nick Martin promised to concentrate on ARM development tools. The Altium acquisitions resulted in the Nanoboards with portable tools across FPGA vendors and a probe that could connect to both Altera and Xilinx (plus with an extra set of “soft” JTAG signals for instrumentation). We tested these on the Digilent S3 board before buying a Nanoboard some years later. I think that the parallel port version shipped with the initial software. The USB version was ordered some years later, but no longer used as Altium battled to keep up with the FPGA vendors' evaluation boards. They gave little away when it came to the embedded probe in the Nanoboard, which was about when we lost interest. These probes also never worked with Altium's Tasking Compilers to debug an ARM core (which Hitex managed with their own probe). In 2012 or 2013, Altium selected the Segger probe to debug a small number of ARM cores with the Tasking Compilers.

Altium JTAG probes on the operating table

Altium JTAG (parallel port and USB) probes on the operating table.

Altium probes up close

Altium probes up-close

Altium JTAG probes. The USB version on the left, the PC parallel port on the right. The switch on the left was to select between Xilinx or Altera FPGAs.

Of the probes that we dissected, the Altium board layout quality was the best. Altium's low-cost instrumentation interface competes with Xilinx' ChipScope, Altera's SignalTap II Embedded Logic Analyzer, and Lattice Semiconductor's Reveal Analyzer.


FPGA Loading

Loading up FPGAs in our proposed designs, plus references are described in “MIPS Concept Design for Software Instrumentation”, written prior to 2006, and saved as IDT574design.pdf (307 kBytes). Have a look at references 4, 5, 7, 17, 20 and 21 (pages 41 and 42) which have hyperlinks to where they were used. The new ARM micro-controllers with large Flash or SD cards would be ideal loaders (some years later).

Circuit diagram of debug header1 for FPGA loading

Debug Header for Xilinx FPGA on MIPS memory board

Circuit diagram of debug header2 for FPGA loading

Debug Header for Xilinx FPGA on MIPS memory board


Circuit diagram of debug header3 for FPGA loading

Debug Header for Xilinx FPGA on IDT574 board

Instrumentation layout

The Virtex FPGAs were SRAM based and had an option to load the configuration over a byte-wide parallel bus. On our 64-bit MIPS board, the multiplexed address/ data bus passed through the FPGA before the static RAM devices. The interception would allow tracing and various tests which would need to be downloaded quickly, as well as uploaded without the target CPU intrusion. Those days are now gone with the CPU disappearing into a package behind peripheral pins and no interface to memory. The tracing vendors with ARM tools have closed the gap considerably over the past ten years, but any serious instrumentation will likely require a FPGA.

The layout has the 50K gate XVC50E, however on the final board a 300k gate device was used (footprint compatible).