Altera FPGA Projects

FPGA on BrightStar ipEngine1 board

Altera 16K gate FPGA on the BrightStar Engineering ipEngine1 board.

We started using Altera FPGAs in 1994 for the MIPS board described in FRD MIPS. The next design for Altera (1999) was an imager interface described in Tread Imager where an Altera Flex 8000 device was used for the decoding and control portion of an image processing board to measuring tyre tread width.

Several Altera designs were done with EP10K devices, and with a 16K gate device on a BrightStar Engineering board. Both schematic capture and VHDL were tested. One of the initial designs for a proposed testbed with a 64-bit MIPS processor was simulated with the design entered via schematic capture for an Altera 100k gate device (interrupt controller, VME bus interface, decoders, debug assistance, serial ports).