CPLD I/O Expander


The board was designed in September, 2002 for testing a 64-bit IDT MIPS design that needded a 32-bit serial bit stream for configuration. Although the on-board FPGA would handle the final MIPS configuration, we needed something easy for board “bring up” that could be tested without too many unknowns. The 32 input switches could be toggled for the processor reset stream, and the processor would then cycle through NOPs programmed into the Flash. Some status outputs on an annunciation panel would help for real-time demonstrations (and the logistics project on the perpetual back burner). The CPLDs would also be useful for general purpose I/O expansion as it had bank selectable voltage levels for the I/O pads (IDT574 was a 2,5 V device).

General Description

Do your boards or processors ever have enough I/O pins? Our’s didn’t either, so we thought about a board with 32 input switches (common for setting Ethernet addresses), plus seventy outputs for driving LEDs. These features are required for many projects, however, the large number of dedicated inputs and outputs for these simple functions increases costs—three additional slots in a backplane, an extra 32-bit input card, two 32-bit output cards, etc.

Of course, they need some way of communicating with the outside world, but do you use I2C or SPI bus? Dedicated I2C or SPI bus chips are not second sourced for byte expansion, plus they do not have much drive capability. They are also designed to connect to a processor within a short distance (not several meters like RS-422 differential drivers).

We chose a simple shift register and “one hot encoding”. The 256 flip-flop device was Flash based and would power-up without requiring a bit-stream before taking on some personality.

Useful Functions

What features could not be provided by dedicated I2C or SPI bus chips?

Simulation for 7-segment

Altera CPLD pick-by-light simulation

The pick-by-light was a potential target. The output was to drive a 7-segment LED display. Entry was via AHDL.

Layout of I/O Expander

Altera CPLD I/O expander layout

The TQFP chip had plenty of pins that we dedicated to I/O. The pin assignment was flexible so a simple PCB could have been manufactured. For prototypes, we chose to use a larger chip as CPLDs don’t have too many flip-flops. The higher flip-flop count devices also tend to have more pins, so we picked a low-cost reasonable sized device and put it onto a four layer board. We had decided some while back to dedicate two layers to signals and two to signal and ground. Board costs were also determined by area (plus holes drilled), so we made it as compact as possible for common functions. The communications signals and reset had not been tested, so we chose to leave the RS-422 buffers (or opto-couplers) off the board. For low-cost connections to the external displays, we used 0,1” pin spacing for ribbon cable.

PCB of I/O Expander

Altera CPLD PCB board

The board was four layers (two signal, power and ground). For the sake of designing a board, a SoC processor would not cost much more for a production product.

Ten years later, Lattice Semiconductor has hardened I2C and SPI blocks in the MachXO2 CPLD with a couple of US$29 evaluation boards in 2011. Even in 2002, it would have been better to use a single chip processor, but we just did not have the time.

Two boards were made—the Altera programmer and the first board were given to a collegue who was busy with postgrad work and needed a simple board for status indication. The PE Technikon paid for the boards and the programmer was left over from the FRD MIPS board in 1994.

Our original goal was to drive the board from the MIPS memory interface card in IDT 574 Aug 02 design. It would be useful for debugging and showing state machine locations when stepping through code. The unbuffered interface to the outside world was via logic levels, so it could not be far from the main board. The shift registers would need periodic resetting to synchronise with the least significant bit, and then to read back what was sent out.

Altera CPLD simulation

The simulated shifting in and out for the remote I/O using Altera simulation tools. The scan was cropped, but the 15uS shown here was run for 72uS, plus several other input conditions.

Altera CPLD PCB circuit diagram



The schematic capture for the board was done in OrCAD.

Altera CPLD PCB circuit diagram



One of the sheets on the internal circuit diagram before the switch to “one-hot” encoding. The diagram was scanned in after a bout of archeology, but the coloured lines were used during simulation and testing. There was a glitch on the output of the circled NOR gate.


Altera’s schematic capture program was used—really impressive.

Examples of I/O Expansion

BetaTech Baseboard with serial I/O on SPI

Betatech QSPI with LEDs

The BetaTech Q-SPI outputs with status LEDs

Betatech QSPI with setup switches

The BetaTech Q-SPI with setup switches

The standard shift registers on the QSPI ports of the ColdFire in the BetaTech Base Board are a better solution compared to our Altera CPLD, as there is local intelligence.

The BetaTech work was done from October to December 2002

Discrete I/O Disadvantages

Large 7-seg displays 100mm high

Large 7-segment LED displays (100mm high)

The large 7 segment displays were driven by discrete outputs, which took 32 outputs (including the decimal places). See Tread Imager or Imager FPGA for a picture of the I/O card that was used to drive two of these cards with 34-way ribbon cable. See connections on the right.

The price difference between single and double layer boards was not much, but the displays could have been mounted in a frame with a small board that connected to the pins. The blank boards were surprisingly expensive due to their large size—certainly more than the cost of a smaller board and dedicated processor.

Discrete Connections

Back of large 7-seg displays 100mm high

Back of large 7-segment LED displays (100mm high)

The buffers on the card that connected to the display used 74AC574 latches that source or sink 24mA. We used a different supply on the remote board and each LED string in the segments had its own transistor and current limiting resistor (I think the panel used 24Vdc and could be seen from twenty meters away). The displays were not multiplexed so that we could get maximum light in the dark tyre plants. This would have been an ideal application for I/O expansion or a small on-board processor.

Related information

For three phase contactors, it would also be advisable to delay switching on, or sequencing certain outputs. On some of the sequenced power supplies in Warwick Smith’s cards in Student Robotic the ramping up was controlled with a small CPLD.

See Input/Output Cards for typical I/O requirements, and where we intend to use local intelligence in a SoC. A simple plug-in card might be a useful product. The first are likely to be intelligent I/O blocks and status boards.

A SoC is a better solution, as it can also indicate to the user when communications have been lost. Although a status board is useful, it is not nearly as useful as one with LEDs on the board! Next time....

Expanded I/O really needs buffering to drive at least a couple of meters and some intelligence to check for transmission errors or lack of communication. For outputs, a benign state would also be useful for wire failures. How do remote outputs power-up? On our board we used the global reset input to the flip flops, but then the outputs would all be off. Maybe that is not desired for active low outputs. If our reset line from the host was not low when the CPLD powered-up, then the outputs could have been anything.

We probably would not use an Ethernet SoC for reading switches or driving status LEDs, and then would not use external shift registers. A high pin-count device with small Flash and RAM would be fine, particularly some of the Energy Micro very low power ARM devices. Additional functions like serial numbers in on-board memory, tamper detection, pulsing power for banks of eight switches, pulsing the LEDs with only one on at a time, and other energy aware tactics.