FPGA Projects

FPGA on Coldfire board

Xilinx Spartan 30K gate with ColdFire on the second BetaTech ColdFire board.

We started using Altera FPGAs in 1994 for the MIPS board described in FRD MIPS. The next design for Altera (1999) was an imager interface described in Tread Imager where an Altera Flex 8000 device was used for the decoding and control portion of an image processing board to measuring tyre tread width. Two boards were made as prototypes, with the first being destroyed by someone deciding to weld on the conveyor without disconnecting the data cables. The bitstream loading also had some issues.

Shortly after the imager design in 1999, we spent nine months contracting at a company doing military work. We were convinced to try out Xilinx FPGAs as one of their designs took over two weeks to synthesize on Altera tools, but ran in a couple of hours on the Xilinx equivalent. The design was sent to Altera for some insight into what went wrong, but it was not resolved during our contracting period.

Prior to FPGAs, from the mid 1980s we used CPLDs or PALs as part of the glue logic for 68000 and MIPS boards. Cypress Semiconductor had a nice package for a PC with a simulator. A universal EPROM-, GAL-, PAL-, and Flash programmer completed the design loop. Later, Altera launched an excellent schematic capture and simulation package, plus they standardised their download cable pinouts.

Several Altera designs were done with EP10K devices, and with a 16K gate device on a BrightStar Engineering board. Both schematic capture and VHDL were tested. One of the initial designs for a proposed testbed with a 64-bit MIPS processor was simulated with the design entered via schematic capture for an Altera 100k gate device (interrupt controller, VME bus interface, decoders, debug assistance, serial ports). A later version used Xilinx 300k gate Virtex parts.

By 2002, we had completed two projects on PowerPC and were interested in tracing a processor for real-time work; the Xilinx Virtex-II with embedded PowerPC and trace port was an ideal combination. As part of a research grant, several Virtex-II Pro boards were ordered for student projects and the academic version of the Xilinx tools. A few JTAG probes completed the tools.

Altium advertised a unified development environment with schematic capture, PCB layout, compilers for several processors, FPGA development, embedded instrumentation and a choice of Altera, Xilinx or Lattice Semiconductor hardware. At the time it was pretty unique, and we bought the package. Later we bought the Nanoboard 3000 with Xilinx for the target.


There are many advantages to FPGAs, however, they are not as easy to debug as marketing departments would have you believe. Single-stepping VHDL is impossible as far as we are aware. Cross-linking onto schematics for a trace, or trace buffers that can be easily triggered take up huge resources requiring a larger device on a board than the final target. We tried to develop peripherals that would be moved across processor families (I2C, serial ports, parallel ports, counters etc.), but the debug effort coupled with the price of configuration memory made it lower cost to simply use a SoC with large amounts of Flash, serial ports, and I2C ports. The SoC did not require debugging at the clock edge level. Intellectual property for an Ethernet port would set you back about $5000, so for prototypes, this was obviously unattractive.

Future Adventures

Xilinx has promised dual ARM cores at respectable frequencies early in 2011 with a core that comes alive before the FPGA fabric, and can boot from external memory. It is August, and hopefully the product sees in the New Year, but we suspect that Moore’s Law has been extended into marketing. See SVS News—25 Aug 2011

We were on a RSS feed and email newsletter from Lattice Semiconductor. In April, 2011 they offered an incredible board for US$99. Xilinx also sent us an email around that time with more information on the Zynq family, so we held off believing it would be launched within a month. We have decided to stick with smaller cores outside an FPGA and design boards around the Lattice Semi EP3 family. Our Versa board should be here early September, 2011.