Virtex MIPS Memory Interface

Virtex MIPS memory interface board

The work was done from 2000 for the IDT 574 and in October 2002 for the trace memory board shown here.

We designed an interface to the MIPS SysAD and SysCMD bus for the 64-bit IDT 574 CPU that could also act as a trace capture unit. Xilinx had provided Verilog examples of a MIPS bus design before we took the plunge, however, technology overtook us, and the MIPS/Lexra patent suite left a sour taste on further MIPS work. Not sure how others felt, but MIPS is slipping off the processor landscape.

We put down a 300K gate device with connectors for a small processor to load up the configuration memory. The Flash chips were designed for Intel, however, when the boards arrived, there was a world-wide shortage and lead-times at the bottom of the dark continent were allocated some exponential curve. We were happy to live on RAM for experimental purposes and populated the boards with 20ns static RAM.

Loading up FPGAs in our proposed designs, plus references are described in “MIPS Concept Design for Software Instrumentation”, last updated 2006. We have included the IDT574design.pdf (307 kBytes) here. Have a look at references 4, 5, 7, 17, 20 and 21 (pages 41 and 42) which have hyperlinks to where they were used. The new ARM micro-controllers with large Flash or SD cards would be ideal loaders (some years later).

During 2002, our interest was in tracing a core to examine a real-time multiprocessor system for post-grad research. MIPS trailed PowerPC and ARM for JTAG or trace ports, so we looked into tracing a stand alone core running uncached code. We wanted to use a 64-bit design as the 32-bit devices were almost the same price. The IDT574 had a 32-bit multiplexed bus, so from a hardware perspective, it would be similar to a 32-bit design. The 64-bit MIPS instruction set was still 32-bits wide. The prior work as documented in the MIPS hardware section had several stabs at a 64-bit system, but it never materialised. We would visit this area between other projects until we could no longer justify the horrid SysAD/CMD bus interface and lack of tool commitment from MIPS. There are chips from Cavium and others that made PowerPC and ARM look pedestrian, but the MIPS ecosystem is no longer as robust as in the 1990s. It is unlikely that we will go back there, even after a huge effort in trying to develop a decent simulator and memory infrastructure.

Unfortunately, even in research, when starting an embedded project at 200 MHz, by the end of a three year journey, technology will be at the 1GHz post. Chasing technology is impractical in an academic or self-funded setting. Anyway, the market seems to favour ARM for embedded work and as we program in C, we don’t care what core is used if the tools are reasonably priced and support source level debugging via JTAG.