Celoxica Demo Platform

 

Celoxica Demo Platform

Celoxica Demo Platform in 2004

 

2004

Around 2004, Professor Theo van Niekerk ordered a Celoxica evaluation system with the Handel-C software. We were given the kit for a few days.

The only documentation we have in 2011 on the board was the Product Description Brochure, dated April, 2004, version 1.0. It described the Platform Developer’s Kit, the Celoxica DK Design Suite, and Platform Support Libraries. Not sure which board the kit was based on, or if the FPGA included a PowerPC core, but we ran the various demonstrations and video tests. We compiled the examples and then had a look at porting the Celoxica Handel-C interface to our other Xilinx boards, and that was when we discovered the “Platform Abstraction Layer” and the wrapper functions that would need to be written. The Xilinx software requirements according to the brochure were EDK 6.1 and ISE 6.1, which we were using at the time on the Virtex-II Pro development and evaluation kits.

We were on a steep learning curve on the Xilinx 6.1 tools and it did not look like Celoxica was giving much away in terms of making the port easy, cheap or relatively painless. Not sure if this was an English company thing, but the Transputer saga was still fresh in our minds, so we put the kit back in the box, thanked Theo and carried on with C and VHDL.

Theo’s workload would increase dramatically as Dean with the Port Elizabeth Technikon and Port Elizabeth University merged to form the Nelson Mandela Metropolitan University. We don’t recall him getting much time with the kit, but the specifications and pre-compiled demonstrations were impressive.


Implementing Image Processing Algorithms on FPGAs

Fast forward to 2011. The IEEE South Australian Computer Chapter arranged a Handel-C course in July, 2011 in Adelaide. The presenter was Asoc Prof Donald Bailey from Massey University, New Zealand. The Computer Chapter hopes to arrange another course in April, 2012.

Celoxica had sold Handel-C to Mentor Graphics some time back, but the competing C-to-hardware compilers have not flooded the FPGA market—yet.

GZIP Compression in Handel-C

We were interested in using Handel-C for trace compression after reading, “Tatari and Celoxica Deliver Fast and Easy Algorithm Acceleration”, by Dale Riley, in the Xilinx Xcell Journal, number 46, pages 38 to 42, 2003. The LZ77 took 40% of a Virtex-II 1000 FPGA and speeds of 133MHz!