Xilinx FPGA Projects


FPGA on Coldfire board

Xilinx Spartan 30K gate with ColdFire on the second BetaTech ColdFire board.

We experimented with several Xilinx FPGAs over the years. Most of our work was on evaluation boards that were low-cost compared to the effort in having to develop similar hardware from scratch. One student project resulted in nine artifacts (Warwick Smith’s M. Tech), most with a FPGA or CPLD. See the Student Robotic page for a snapshot of what hardware can be developed in just over a year on a student project. There were other boards for PowerPC work, plus all the hardware was debugged and tested in VHDL.

In 2000, we were given a Virtex demo board which was programmable using free versions of Xilinx tools. See Demo board. Xilinx offered to supply single quantities for prototyping, which was a welcome relief when other silicon merchants had large MOQs. The years from 2000 to 2006 were spent on several Xilinx projects using VHDL. We drifted back to working on processors in the wild that were a lot faster than those captured in FPGAs, and did not bother with VHDL since then.

The choice of FPGA is largely driven by customers. The technology is extremely fast moving with expensive tools for customers without academic pricing. The vendors’ tools are often subsidised or locked to a board. For ease of reconfiguration and I/O expansion, there is little to compare to a FPGA. We were always interested in the FPGA as a slave to a processor core. The loading up was also not that easy in an embedded target, as we found out in our Tread Imager project.

There are several Xilinx FPGA projects that can be referenced from this page. Future work in FPGAs will be for an instrumented testbed that might become a product. The web pages placed here are for historical purposes. Future design efforts will need a Wiki or proper manuals. It also will not happen in 2011—the rest of this year has been accounted for. We will be using Verilog on some Lattice Semi boards this year and look forward to the Xilinx Zynq launch.