MIPS Design on VME for FRD

FRD Timeline

A RISC board was designed as part of an effort to develop a low-cost, public domain VME platform in 1995 (ZAR2000 or $550). The board would be software compatible with the 32-bit RISC IDT381 and IDT385 evaluation platforms. (The FRD was South Africa’s Foundation for Research Development)

This page lists the board specifications, project partners, sources of funding, and documentation (Talk at Rhodes University (122kB pdf), and the report-back meeting.


The research proposal required industry and academic collaboration. A joint project was proposed with Dr. Gil Klintworth of Mecalc in Pretoria, the Leather Research Institute at Rhodes University in Grahamstown, the Computer Science Department at Rhodes, and B.Tech student projects in Digital Systems at Port Elizabeth Technikon. More details1 of the project are available here, Talk at Rhodes University (122kB pdf), which described the design and the architecture selection.

After borrowing a Radstone MIPS board from Mecalc, the South African agent, we discovered that the board was being phased out as IDT changed the packaging for the 3081 processor. This meant that future IDT MIPS work would need an alternative board. Several people expressed an interest in a locally available, low-cost board. The FRD was approached for a grant of R100,000 in September, 1994, which was approved 1st December, 1994, but only for R20,000. There was not enough money to purchase the Radstone board, as VME boards typically cost more than R20,000. The Radstone board did not have schematics, source code for a monitor, a recent VxWorks port, or PC based software development. The price was too much for the other partners, and I would rather spend my own money on a workstation. For automation work, the commercial VME boards were simply too expensive. I decided to go ahead with the design. The loan of the Radstone board was a huge help, as Algorithmics’ documentation was excellent. Not much could taken from the VxWorks port other than the board support package, which indicated that many of the bus interface functions were disabled in the VIC/VAC068 chips—as they were really designed for 68020 and above processors. The VIC/VAC chips assumed that J2 was available for the upper 16-bits of the 32-bit data bus with extra address lines.


YearNumber of projectsAmount allocated
19912Rl50 000
19927R480 000
199322Rl 495 000
199433Rl 860 000
199544Rl 610 000

FRD Funding3

The change of government in 1994 in South Africa resulted in a change of focus to address poverty. Education funding was to undergo major changes. This programme was cancelled three months into the project after receiving funding. This contributed to the lack of enthusium as no grantees were using VME or MIPS processors. More than a paper design would be necessary to really test interest.

In the above table, the last row was “as at 31 March 1995”. In4 “The new FRD programmes will be formally announced by July 1995.” Further on, “All current FRD programmes will be concluded by 31 December 1995”. The total USD equivalent for this programme in 1995 was US$443 526 using the average exchange rate of R3,63 to the US dollar. My allocation of R20,000 (US$5509), was spent on:

The balance of R6884 was to be used to manufacture the printed circuit boards, which never happened as the funding evaporated (not sure where it went, or if the FRD ever sent the final amount. Perhaps it was kept to pay for flights, accommodation and transport at the report-back). In all, only $1294 was actually used (including 14% sales tax).


The design had been on paper for some time (can't remember exactly when it started, but I had been using the IDT385 evaluation board for over a year). The dates were taken from printouts of the design, which favours latest revisions as older papers are thrown away. The schematic capture was completed in February, 1995, partial layout by April.

To put the technology into perspective, in 1995, the P54C Pentiums were clocked at 120 to 133 MHz with a bus speed at well below 100 MHz, still running 16-bit Windows 3.1. My last Transputer T805 board ran at 20 MHz, and this board was designed for good performance at low clock speeds.

Grantees Report Presentation

The presentations2 were largely run in parallel. The only audience in a slot before- or after tea would be the other presenters in the same slot. Industry participants were not going to spend two days away from the office to see what might pop out of research. I am not sure how well the presentations were advertised or if industry were invited.

Academic projects need to be short to publish at least once a year, which does not encourage long-term hardware development if “off-the-shelf” is available or could be produced by lesser qualified beings. Many of the projects were for investigating manufacturing processes or workflows; few actually developed hardware. Those who did, produced hardware designs for 8051 boards. This is to be expected for undergrad projects with 13 week semesters and little- or no budget. See prior 8031 boards here 8031 student boards


1 Ian Clark, (1995, 5th April), Low Cost RISC Processor Card for Educational Institutions and Factory Automation, “Monthly talks” at the Computer Science Department, Rhodes University, Grahamstown, South Africa. A copy scanned in and pushed through LaTeX in 2010 to generate a PDF is available here 122 kBytes talk95.pdf with some added information that only fifteen years of hindsight can provide! companies95.pdf
2 Ian Clark (1995 13—14th Sep), Development of a hardware and software platform for the monitoring and control of multiple tannery drums, FRD Programme on Expertise and Human Resources in Manufacturing Technology, Fourth FRD Grantees Report-Back Seminar, pp 48—50, Rand Afrikaans University, Johannesburg, South Africa
3 Booklet handed out at2, third page (not numbered).
4 Booklet handed out at2, last page and inside back cover.
5 The reason for not purchasing the Indy workstation was that the Indy was already 18 months old, which was typically a generation in workstation land. New MIPS chips were announced some time back. When the local sales person was asked about the next generation, we were accused of discovering inside information, and wanted to know our sources! The Indy or its successor were never purchased. I had already received a monochrome Sun workstation previously that was the same price as a newer 2× faster colour model announced two weeks later, so “once bitten, twice shy”!

Board Layout

MIPS FRD board

Figure 1: Top and bottom signal layers of IDT3081 MIPS board designed and laid out in 1995 by Ian Clark.

MIPS FRD Silkscreen

Figure 2: Top silkscreen. This file was updated in 1997.

MIPS FRD schematic

Figure 3: The initial schematic capture was done in OrCAD in February, 1995. Some time later, I updated the package and tried to resurrect the MIPS design for the Tyre Imager in April, 2000. The timelines became too tight after the main contractor and end-user took so long to decide on the imager proposal. (Like so often in the embedded development work, you get less time to do a design than the customer takes to write out an order—or pay!) The left hand side near the processor has a missing resistor pullup package. A couple of library parts were missing in the CAD upgrade.

The original design used OrCAD and was read into Altium a couple of years later to create the PDF, which is available here as a PDF (3,1Meg). Some lables and a few pullup resistors never made it in the conversion. The design was meant to be open source, so feel free to use it for whatever purposes. The complete board (160 × 234mm) would later fit into a SoC less than 20 years later — updated this page in 2016 in response to a request for the design files. We tried to download an OrCAD viewer, but the formats vary so much over the years that the later software cannot open earlier files, besides, we cannot find the board layout files.