IDT 574 January 2001 Design

Photo of 128-pin TQFP package

The 128-pin 64-bit CPU

IDT574 CPU schematic capture

In 2000, we upgraded our OrCAD tools and evaluated the Cadence Allegro auto-routing package. The 128 pin TQFP device was pretty simple—almost half the pins were for power (3,3V and 2,5V, ground pins), a mutliplexed 32-bit address and data bus, the infamous SysCMD bus, some interrupt signals, the serial configuration pins and JTAG pins (not for software debug).

The memory and Xilinx Virtex-E interface (not shown here) were fairly modest for a 64-bit processor. The Flash would be programmed via the FPGA and handle the booting from 8- or 16-bit wide Flash to 32-bit instruction access. We’ll post a PDF of the design as part of the structured publishing conversion process. The above design never made it into the wild; it was part of some self-funded reseach.