IDT 574 July 2001 Design

Photo of 128-pin TQFP package

The 128-pin 64-bit CPU

The July 2001 IDT574 MIPS design never escaped from the hard drive. The chip was becoming less attractive as obsolescence creeps in very quickly in electronics. Any industrial applications would need Ethernet and graphics, particularly if requiring 64-bits.

IDT574 CPU with Xilinx FPGA placement

The Altera EP1K100 FPGA in the June 2001 Design was too small for the numerous serial ports with large buffers and transceiver control, plus interrupt controllers, etc. The MIPS SysAD/ SysCMD commercial interface ASICs handled dynamic RAM refresh, but we chose to use static RAM for our first FPGA iteration. The large Xilinx FPGA top-level design was done in schematic capture with the lower levels in VHDL (mostly from application notes and the OpenCores website). Large serial Flash chips were added for data logging of the underground radar project, as debugging in a coal mine could only be done in a non-explosive environment, so we saved as much as possible for post-mortem tests.

The neurosurgery imaging grant had been approved and resources would need juggling with the golf-, tennis-, cricket-, mining- and other radar projects. After discussions with imaging experts at UCT, and a masters student from electronic engineering (who laid out a Galileo Technology GT-641xx and IDT574 compatible board, and I think Ethernet), the project seemed back on track. UCT had ported 64-bit Linux to their IDT574 boards and were running a Beo-Wolf cluster. The project supervisor offered to assist with IDT574 design and Linux work at rates that made it attractive to simply go and purchase a Momentum Computer RM7000 board. The masters student was close to writing up and his supervisor was writing up a PhD, so neither one could really offer significant time. Intellectual property issues were not clear and the golfing or tennis radar project would need full control over rights. Management estimated that to debug the partially laid out board shown above was going to take two months including turn-around times for PCB layout, manufacture, population, porting a real-time kernel, etc. Even if we could manage in two months, we simply ran out of time.