MIPS Projects

MIPS was promoted as a successor to the 68000 processor for embedded work. In the early 1990s, this looked possible—numerous academic projects, papers, adoption in some of the most appealing workstations from SGI and DEC. Clock rates were easy to work with compared to higher clocked 68040 devices at similar performance.

We worked on several MIPS projects interspersed with PowerPC and other commercial work. The move to 64-bits was likely to be easier on MIPS, as the IDT 79RC64574 was available in a 128 pin TQFP with a 32-bit multiplexed bus. There was no similar device for PowerPC, SPARC or ARM.

The links on the menu bar above document the MIPS related work. There are other MIPS projects to document, but to prevent broken links, they’re not up yet. They are:

Modest Package Requirements

Package from PLCC to TQFP

The IDT MIPS devices had modest packages, even for a 64-bit processor. Packages: 84 pin PLCC top and bottom (3041), Pin-grid-array (3081), 128 pin TQFP (79RC64574 64-bit). All same scale.