Altium TSK3000A Soft Core

Altium’s TSK3000A soft core was not supplied in a format that would allow modifications. There was a menu front-end that allowed different sized cache and other features. See Altium’s TSK3000A 32-bit RISC Processor, which was dated July 15, 2006. On a Google search, much of the other TSK documentation is 2008 or earlier. Although the documentation does not specifically mention MIPS, the core looks like the DLX or MIPS-I core. We remember the farce with the Lexra case of the unaligned instructions and the patents that had plenty of prior art (but were not revoked) and the eventual demise of Lexra, so not surprising that there is no mention of MIPS.

We wrote a MIPS simulator and a memory program, but were caught out on how the delay slot would work and what if there were two branches in a row. (We had to cater for the possibility as we could not assume that a compiler augmented with hand-written assembler would not have a branch within a delay slot). Not so useful anymore, but in the 1980s this was a good arguement for having a useful instruction to execute even if a branch would flush the read-ahead buffer or cache. With simultaneous multi-threading, superscalar and other techniques with up to 80 in-flight instructions and register renaming, the delay slot is a hinderance. Altium has not really done much with the core and the frequency is low when compiling the netlist. MIPS themselves have not executed well either, and the FS2 acquisition with some patents around debug do not bode well for anyone wanting to tread around here without a MIPS licence. We will stick to companies that had university programs with academic licenses or low-cost source code. The MIPS core that was posted by Steve Rhoads’ Plasma project around 2001 was useful for the instruction set mapping.

FPGA on Altium Nano3000 board

Xilinx Spartan 3AN FPGA on the Altium Nanoboard 3000


According to the updated posting on Steve Rhoads website, the MIPS unaligned instruction patents expired on 23rd December, 2006. NetLogic, Cavium and others have very capable multicore MIPS devices, so perhaps this might be of interest to you for MIPS adventures.

As mentioned elsewhere, we were always after network and display capabilities, and these are well catered for by many ARM SoC devices. We are unlikely to return to MIPS based designs.