Z8000 Static Tester

Z8001 static testing on Eurocard wire wrap board

Static testing a Z8001 wire wrap board around 1983.


Several Multibus I boards were purchased from the local National Semiconductor agent in Cape Town—card cage, backplane, extender board and wire wrap prototyping boards. As part of the testing, a static version of the Zilog Z8001 processor was placed on the lower board and the “pod equivalent” inserted into the target processor socket on the board to be tested. (Plugged into the extender card for easy probing). A state machine was programmed into EPROM so that invalid states could not be set during testing (ie. cannot read and write at the same time). The hex displays showed the 24-bit address bus, the 16-bit data bus and decoded status LEDs for the control signals. This allowed the target’s address decoding, data buffer direction control and boot sequence to be tested. Simple “glue logic” was placed into PALs or GALs, which was also statically tested.

Between the static testing board and the target socket, another board provided connectors for either a Z8001 (48 pin) or Z8002 (40 pin) processor. The interface boards were also designed to read the target with a test clip over a processor in the target. This allowed the target to be single stepped with the address and data displayed on the hex displays. Address comparators also allowed the target to stop on a ‘breakpoint’ where the user could single step further. In the foreground, a Hewlett Packard logic probe, pulser and current trace were used to track down problems. The switches were for toggling control signals if enabled for static tests, or for matching comparators to trigger an oscilloscope or breakpoint circuit.

Z8002 static testing on Multibus I wire wrap board

After the static tests, EPROMs were programmed with several thousand sequences of NOP instructions and a jump at the end back to the beginning of the loop. The repetitive pattern was easy to trigger on, making timing diagram verification with a four channel oscilloscope possible.