April News


Image Processing/FPGA Course

From the 18th to the 20th April, the South Australian IEEE Computer Chapter invited Associate Professor Donald Bailey, from Massey University in New Zealand, to present a course — “Implementing Image Processing Algorithms on FPGAs”. The course was held on the Mawson Lakes campus, (University of South Australia), in Adelaide. The same course was run in July, 2011, also at the Mawson Lakes campus. The fast paced course was excellent, providing “hands-on” tutorials in Handel-C to target an Altera FPGA. Many of the sixteen attendees were employed in the field of image processing or FPGA-based design. Others wanted to compare hardware—software codesign, or benefits of FPGA hardware versus software on GPUs and DSPs. After a brief introduction into VHDL, the course was based on the Handel-C language to create the FPGA designs. At the low-level pixel processing, the examples clearly demonstrated the Handel-C and FPGA advantages versus trying to meet timing constraints on any desktop software approach. The modest video pixel clock rate of 25 MHz only leaves 40 ns per pixel for stream processing.

For an impressive publications list, visit the Massey University SEAT Home page


Course Notes with the Handel-C examples and tutorials.

Donald Bailey notes

You would be hard pressed to find a better short course on either FPGAs or imaging, with original intellectual property to use in your own designs. The book obviously goes into more theoretical details on imaging, and compliments the course nicely. Writing in a C dialect to generate hardware really works. Not a believer? — then try and get onto a future course.

Gold mine of information

Donald Bailey book

Donald G. Bailey's excellent book “Design for Embedded Image Processing on FPGAs”, published by John Wiley & Sons (Asia) Pte. Ltd., 2011. ISBN: 978-0-047-82849-6.

Note: The book was published before last year's course was developed, so the sample Handel-C code is not part of the book.

Image Processing Hardware

Each attendee had their own workstation with an additional screen to attach the video output from the FPGA board. The boards were supplied as part of the course fees.

TerasIC DE0 FPGA board

TerasIC DE0 board with Altera Cyclone III FPGA and camera plugged-in.

TerasIC camera board

5 mega pixel D5M camera from TerasIC.


Rest of April

The rest of April was spent updating the website, some TI Luminary Micro (ARM Cortex-M3/M4) software development, a touch of Verilog for the TerasIC board, and office renovations.